EDN

Wafer Level Chip Size Package

This application note provides guidelines for the use of Wafer Level Chip Size Packages (WLCSP). The information in this application note can be used throughout the various stages of WLCSP use. This ...
Business Wire

Research and Markets: Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate - The Next Generation of IC Packaging & Substrate Assembly Waves

Things are moving really fast at the moment as this year, we see both Fan-out wafer level packaging and chip embedding into PCB laminate infrastructures emerging at the same time, ramping to high ...
Seeking Alpha

Aehr Seeing Momentum in Package-Level Burn-In Alongside Expanding Wafer-Level Burn-in Demand

FREMONT, CA / ACCESS Newswire / November 12, 2025 / Aehr Test Systems (AEHR), a worldwide supplier of semiconductor test and burn-in solutions, today announced the shipment of its Dual-Echo™ test and ...
Electronic Design

Wafer-Level Chip-Scale Package Favors Small-Form-Factor ASICs

A fully qualified, high-performance, low-power and small-form-factor wafer-level chip-scale package (W-CSP) developed by Oki Semiconductor satisfies a wide range of ASIC design demands. Targeting chip ...
Electronic Design

Microchip Expands UNI/O EEPROM Line With Wafer-Level Chip-Scale And TO-92 Packages

Microchip has developed a single-I/O bus UNI/O EEPROM devices in miniature, wafer-level chip-scale and TO-92 packages, in addition to the 3-pin SOT-23 package. Measuring 0.85 mm x 1.38 mm, the ...
Semiconductor Engineering

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution

A look at design considerations for a double-sided RDL, including board-level reliability and the challenges of higher density. System-in-Package (SiP) technology continues to be essential for higher ...
Houston Chronicle

(BW) Wafer-Level Packaging Requirements Boost Orders for Jordan Valley Semiconductors' Advanced X-ray Metrology Systems

Semiconductor metrology equipment manufacturer Jordan Valley Semiconductors announced that they have sold, installed and qualified multiple units of their JVX 6200 system to leading memory ...
Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Semiconductor Engineering

Easing The Stress For Package-Level Burn-In

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and ...

Aehr Receives $14 Million Order from Lead AI Processor Customer for Multiple New Fully Automated FOX-XP Wafer Level Burn-In Systems

FREMONT, CA / ACCESS Newswire / February 26, 2026 / Aehr Test Systems (NASDAQ:AEHR), a leading provider of test and burn-in ...
EDN

Wafer Level Chip Size Package (WLCSP) Guidelines

This application note presents the Wafer Level Chip Size Packages (WLCSP) guidelines. The method uses ball drop bumps with bump pitches of 500 µm and 400 µm and plated bumps with bump pitches of 400 ...