Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively.

Current specification flows often use standard text processors to capture formal register and memory map information of hardware designs along with other less formal types of specification text.

Standardization work is underway to develop assertion languages (for example, PSL and SystemVerilog Assertions) to address the shortcomings of natural language specification. The goal in creating ...